速度反馈信号的检测和处理

Application of Digital Phase-locked Loop Technology in Meterage Speed of Motor

通过几种速度反馈信号检测方法的比较 ,介绍了全数字锁相环测速方法的优点 ,详细讨论了如何在FPGA中利用Verilog语言实现全数字锁相测速方案和通过锁相环DPLL中可逆计数器模值的可修改特性 ,来控制DPLL的跟踪补偿和锁定时间 ,DPLL的中心频率可调以及消除“纹波”

Compared some technic of meterage speed of motor. This paper discusses how to implement a lead lag DPLL in Verilog with a ALTERA'S CPLD to recover the speed of an motor and through the reversible counter to justed the ceter frequence of DPLL,change the mode number to control the phase retrieve. The effect of the loop's architecture parameters on its performance is indicated observe