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基于时间约束的FPGA数字水印 被引量：1

FPGA Watermarking Based on Modification of Time Constraints
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摘要 该文提出一种基于时间约束的FPGA数字水印技术,其基本思想是将准备好的水印标记嵌入非关键路径上的时间约束来定制最终的下载比特流文件,同时并不改变设计的原始性能.这一方法能保证水印标记所对应的下载比特流文件的唯一性,从而可对FPGA设计模块的所有权提供强有力的证明。与其他方法相比,该文提出的技术不仅具有零空间开销和低时间开销,而且还有效地提高了信息嵌入量。 Based on modification of time constraints in the FPGA design, a watermark-embedding scheme is proposed for protection of intellectual property rights of the system designer. A coded binary watermark sequence is used to replace the least significant digits of the time constraints in some non-critical paths. The modified time constraints lead to substantial and unique changes in the generated bit stream without altering the performance of the design, both in terms of space and time overheads and the system functionality. The embedded data can be extracted in a reverse procedure. The paper provides a scheme with zero area and low timing overheads, and a significant increase in embedding capacity in comparison with some existing techniques.
作者 陆健峰 王朔中
机构地区 上海大学通信与信息工程学院
出处 《电子与信息学报》 EI CSCD 北大核心 2004年第12期1882-1887,共6页 Journal of Electronics & Information Technology
基金 上海市重点学科建设项目(2001-44)资助课题
关键词 知识产权 数字水印 现场可编程门阵列 时间约束 <Keyword>Intellectual Property Right (IPR), Digital watermarking, Field Programmable Gate Array (FPGA), Time constraint
分类号 TP391 [自动化与计算机技术—计算机应用技术]
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参考文献13

  • 1[1]Petitcolas F A P, Anderson R J, Kuhn M G. Information hiding - A survey. Proc. IEEE, 1999,87(7): 1062-1078.
  • 2[2]Hartung F, Kutter M. Multimedia watermarking techniques. Proc. IEEE, 1999, 87(7): 1079-1107.
  • 3[3]Lach J, Mangione-Smith W H, Potkonjak M. Signature hiding techniques for FPGA intellectual property protection. International Conference on Computer-Aided Design, San Jose, CA, USA,1998: 186-189.
  • 4[4]Kahng A B, et al.. Watermarking techniques for intellectual property protection. Design Automation Conference, San Francico, California, USA, 1998: 776-781.
  • 5[5]Lach J, Mangione-Smith W H, Potkonjak M. Fingerprinting digital circuits on programmable hardware. International Workshop on Information Hiding, Portland, Oregon, USA, 1998: 16-31.
  • 6[6]Lach J, Mangione-Smith W H, Potkonjak M. Fingerprinting techniques for field programmable gate array intellectual property protection. IEEE Trans. on Computer-Aided Design, 2001,20(10): 1253-1261.
  • 7[7]Lach J, Mangione-Smith W H, Potkonjak M. Robust FPGA intellectual property protection through multiple small watermarks. Design Automation Conference, New Orleans, LA, USA,1999: 831-836.
  • 8[8]Lach J, Mangione-Smith W H, Potkonjak M. Enhanced intellectual property protection for digital circuits on programmable hardware, International Workshop on Information Hiding, Dresden,Germany, 1999: 286-301.
  • 9[9]Kahng A B, et al.. Constraint-based watermarking techniques for design IP protection. IEEE Trans. on Computer-Aided Design, 2001, 20(10): 1236-1252.
  • 10[10]Jain A K, Yuan Lin, Pari P R, Qu G. Zero overhead watermarking technique for FPGA designs.GLSVLSI, Washington, DC, USA, 2003: 147-152.

同被引文献14

  • 1苗胜,戴冠中,慕德俊,李美峰.基于FPGA的IP核水印保护方法[J].微电子学与计算机,2007,24(3):30-33. 被引量：6
  • 2李东晓,郑伟,张明.IP芯核水印技术研究进展[J].电路与系统学报,2007,12(4):85-92. 被引量：5
  • 3Chang H, Cook L.Surviving the SOC revolution: a guide to platform-based design[M].Norwel, MA: Kluwer Aca- demic Publishers, 1999.
  • 4Liang Wei, Zhang Dafang, You Zhiqiang, et al.A survey of techniques for VLSI IP protection[J].Information Tech- nology Journal,2013,12(12) :2324-2332.
  • 5Long Jing,Liang Wei,Xu Jianbo.An FPGA-based distrib- uted IP watermarking method[C]//Proceedings of 2011 International Conference on Electronical & Machanical Engineering,2011 : 1715-1717.
  • 6Xu Jianbo, Long Jing, Liang Wei.A DFA-based distributed IP watermarking method using data compression tech- nique[J].Journal of Convergence Information Technology, 2011,6(8)-152-160.
  • 7Schmid M, Ziener D, Teich J.Netlist-level IP protection by watermarking for LUT-based FPGAs[C]//Proc of IEEE International Conference on Field-Programmable Technology, 2008:209-216.
  • 8Lach J, Mangione-Smith W H, Potkonjak M.Signature hiding techniques for FPGA intellectual property protec- tion[C]//IEEE/ACM International Conference on Computer- Aided Design, 1998: 186-189.
  • 9Ziener D, Baueregger F, Teich J.Using the power side channel of FPGAs for communication[C]//Proceedings of the 2010 18th IEEE Annual International Sympo- sium on Field-Programmable Custom Computing Machines. Washington DC : IEEE Computer Society, 2010: 237-244.
  • 10Cui A, Chang H,Tahar S.A robust FSM watermarking scheme for IP protection of sequential circuit design[J]. IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems,2011 : 678-690.

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电子与信息学报
2004年 第12期

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