低信噪比图像序列能量积累的硬件实现

Hardware implementation of low SNR image sequences energy accumulation

讨论了两种常用的低信噪比图像序列能量累加算法,一种是针对帧间运动速度较小的多帧累加;一种是针对帧间运动速度较大的形态膨胀累加,并给出了这两种算法的FPGA电路实现框图。实验结果表明,设计的电路结构简单、流程清晰、实时性强、外部器件少、可扩展、可移植,并在实际应用中取得了较好的效果。

Two low SNR image sequences energy accumulation algorithms in common use are discussed. One is multi-frames cumulating aiming at slow moving targets, the other is morphological dilation-cumulating aiming at fast moving targets. The hardware implementation based on FPGA of these two algorithms are presented. Experimental result shows that the design has simple structure, clear flow, high running frequency, less periphery components, good expansibility, portability, and has been successfully applied in IR information processor.