HDLC协议处理器的FPGA实现

Hardware Implementation of HDLC Processor with FPGA

讲述了一种HDLC协议的硬件设计实现,并在FPGA上成功地实现了综合。全部设计方案采用VHDL语言描述。实验结果证明这种设计有效可行,可以满足一些系统的要求。对HDLC功能设计采用的是“ToptoDown”(“从顶到底”)的方法,根据要求的功能先设计出顶层的原理框图,由若干个功能模块组成。再把各个模块细化为子模块,各层的功能用硬件描述语言来实现。设计采用分块处理的方法使各个模块的设计简单灵活、易于修改,适合中小批量通信产品的设计。

In this paper,a reasonable logic structure for HDLC Processor is described and the design has been implemented in FPGA.The whole scheme is described in the VHSIC Hardware Description Language (VHDL).The results show the design is attractive for use in some applications.HDLC Processor is designed and adopted by 'Top to Down' method.The top principle block diagram is designed by the required function,which is made up of several function modules.Every layer of functions is realized with the hardware description language,which made design simple and flexible,easy to revise,suitable for design of the communication products on short run.