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HDTV信源解码SoC中解复用的设计与实现

Design and Implementation of TSD in HDTV Source Decoder SoC
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摘要 结合高清晰度电视(HDTV)SoC平台项目,重点研究了HDTVSoC平台中一个重要功能模块MPEG-2传送流(TS)解复用的设计与实现过程。实验证明本模块TS流处理速度可以达到120Mbps,完全满足HDTV解码需要。 Combined with the project of HDTV SoC platform, the design and implementation of MPEG-2 transport stream de-multiplexer is studied as a major point, which is an important functional module in HDTV SoC platform. Experimental results show that the transport stream processing speed of this module is up to 120 Mbps.
出处 《电视技术》 北大核心 2005年第8期49-51,共3页 Video Engineering
基金 国家"八六三"计划资助项目(课题编号:2003AA1Z1070)
关键词 高清晰度电视 SOC 解复用 MPEG-2标准 HDTV SoC demultiplex MPEG-2
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  • 1Lei Jinmei,Yao Qingdong. Software/hardware co-design for system on chip[C]. The Fourth International Workshop on CSCW in Design. Compiegne, France: 1999:237 - 240.
  • 2Rowson A. Hardware/software co-simulation[C]. The 31^st Design Automation Conference. San Diego, CA, USA, 1994:439 - 440.
  • 3Zhu Jianwen, Gajski D. An ultra-fast instruction set simulator.IEEE Trans. on Very Large Scale Integration (VLSI) Systems[J],2002, 10(3): 363 - 373.
  • 4ARM Limited. ARM7TDMI Data Sheet. ARM DDI 0029E,http://www. ann.com/documentation/, 2002.
  • 5Liu Jie, Lajolo M, Sangiovanni-Vincentelli. Software timing analysis using HW/SW cosimulation and instruction set simulator [C]. The International Workshop on HW/SW Codesign. Seattle,WA, USA, 1998:65 - 69.
  • 6吴清平,刘明业.VHDL事件驱动模拟核心库[J].计算机研究与发展,2002,39(1):17-22. 被引量:3

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