摘要
本文介绍自动抄表系统的原理,用VHDL语言编写抄表器模块,以FPGA作为硬件载体,具有集成度高、功耗低、灵活性等优点,仿真表明该方案是可行性的。
This paper introduces the principle of the automatic water meter, designs the module of Reading Instrument with VHDL ; implementing with FPGA has the merit of high integration, low power, agility and so on ,simulation shows the scheme is reasonable.
出处
《科技广场》
2006年第4期122-123,共2页
Science Mosaic