光纤通信用低相位抖动时钟数据恢复电路

A high-speed and low-jitter CDR circuit for fiber-optic communications

文章阐述了一种适用于光纤通信的锁相环（PLL）时钟数据恢复电路结构。该结构采用负阻放大形式构成二阶有源低通滤波器，并用PECL环形延时单元构成压控振荡器（VCO），工作在80-500MHz的频率范围内，峰-峰相位抖动〈20ps，锁定时间〈600ns。实际电路在计算机上仿真成功，版图后仿真验证也已通过，并进行了投片。

A low-jitter PLL CDR circuit for fiber-optic communications is introduced, which adopts a second-order active LP filter using negative-impedance amplification and forms a VCO with PECL ring time-delay elements, operating within the range of 80 - 500 MHz with the peak-peak jitter 〈 20 ps and the phase-lock time 〈 600 ns. Both pre- and post-layout simulations of the actual circuit prove to be successful.