一种8位250 MHz采样保持电路的设计

Design of an 8-Bit 250 MHz Sample-and-Hold Circuit

介绍了一种采用0.35μm BiCMOS工艺的双路双差分采样保持电路。该电路分辨率为8位,采样率达到250 MSPS。该电路新颖的特点为利用交替工作方式,降低了电路对速度的要求。经过电路模拟仿真,在250 MSPS,输入信号为Vp-p=1 V,电源电压3.3 V时,信噪比(SNR)为55.8 dB,积分线性误差(INL)和微分线性误差(DNL)均小于8位A/D转换器的±0.2 LSB,电源电流为28 mA。样品测试结果:SNR为47.6 dB,INL、DNL小于8位A/D转换器的±0.8 LSB。

A 0. 35 μm BiCMOS dual-path-dual-difference sample-and hold circuit is presented, which has achieved an 8-bit resolution and 250 MSPS sampling rate. By means of alternate working mode, it brings down the demand for speed. Simulation shows that, with 1 V input and 3.3 V voltage supply, the circuit has an SNR of 55.8 dB, an INL and DNL less than ±0.2 LSB, at the sampling rate of 250 MSPS, and its current supply is 28 mA. Test results of the sample circuit indicate that an SNR of 47.6 dB, an INL and DNL less than that of 8-bit ADC, which is ±0.8 LSB, have been achieved.