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一种有利于硬件实现的LDPC码的研究

A Research on Low Density Parity Check Codes Convenient for Hardware Realization
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摘要 本文根据LDPC的编译码原理,提出一种新颖的有利于硬件实现的编译码结构。这种译码结构采用准循环的编码构造方法,对于在计算和存储方面较为便利,采用简化的译码算法,硬件实现简单,且编码增益较高,所有的性能在BPSK调制和AWGN信道中得到估值。 According to the principle of LDPC coding and decoding, this paper presents a new coding-and-decoding structure convenient for hardware realization. This structure adopts quasi-cyclic structuring ways which are convenient for calculation and storage. Adopting simplified decoding algorithm, the hardware realization is relatively simple. Moreover, the coding plus is high. All the performances are evaluated over the AWGN channel with BPSK modulation.
出处 《江西科技师范学院学报》 2006年第4期96-99,共4页 Journal of Nanchang Vocational & Technical Techers' College
基金 江西省重点科技工业攻关项目。课题编号:200210030
关键词 LDPC码 BP算法 编码增益 max-log-map译码 LDPC codes BP decoding algorithm coding plus max-log-map decoding
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参考文献6

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