基于现场可编程门阵列的新型纠错码实现方案

Implementation of a New Correct Code Based on Field Programmable Gate Array

低密度奇偶校验码(LDPC)是一种具有稀疏校验矩阵的线性分组纠错码,它具有逼近香农限的性能,其译码采用迭代译码算法。提出了利用现场可编程门阵列FPGA技术实现数字信号处理可以很好地解决并行性、可配置性和速度问题。给出了一种基于LDPC译码器的FPGA硬件实现方案,其算法的关键是变量节点和校验节点间的信息传递。

Low Density Parity Check （LDPC） Code is one kind of liner block correct codes with low density parity matrix, which capacity is closely to the Shannon limit. The decoding of LDPC Code is iterative. Suggesting that the implementation of digital signal processing using Field Programmable Gate Array （FPGA） can solve problems including parallel architecture, configurationality and speed. Giving a scheme of how to implement LDPC decoder based on FPGA. The key of it is the information transfer between bit nodes and check nodes.