基于FPGA的DDC中抽取滤波系统的设计

Design of Decimation Filter System for DDC Based on FPGA

探讨了DDC中抽取滤波系统的设计方法和基于DSP Builder的具体实现方案,采用CIC滤波器、HB滤波器、FIR滤波器三级级联的方式来降低采样率,并进行了模型仿真,结果表明设计是可行的。

This paper describes the system of decimation filter and implementing method based on DSP Builder ,Through the cascade of CIC fiher,HB filter and FIR filters,the data frequency is cut down,simulation results verify that design of this filter system is feasible.