摘要
描述了一种光纤通信系统中基于FPGA实现的时钟提取电路的原理,在MAX+PLUSⅡ环境下结合原理图和进行了综合、仿真和配置,该电路实现了时钟提取电路的全数字化。测试结果表明,该设计方法能比较准确地恢复时钟信号。
The principle of a digital communication clock circuit based on FPGA in optical communication is described. Then using MAX ＋ PLUS Ⅱ software, colligation, simulation and synthesis are realized on the basis of the graphic editor. The design digitizes the clock circuit. Test results show that the design method restores clock signals more accurately.
出处
《电子科技》
2008年第12期28-30,共3页
Electronic Science and Technology
基金
山东省科技攻关项目(2005GG4201002)
关键词
位同步
FPGA
数字锁相
bit synchronization
FPGA
digital lock phase
