一种融合FPGA和ISS技术的软硬件协同验证方法

Hardware/Software co-verification solution integrated FPGA and ISS

建立了一种基于硬件加速器FPGA和指令集模拟器ISS对嵌入式系统功能进行软硬件协同验证的方法。针对此方法的实现,分析了协同验证过程中软硬件交互技术,并给出总线功能模型BFM结构及其实现方法。经实例验证分析表明,基于FPGA和ISS的协同验证方法,在对嵌入式应用系统验证中与其他几种常用方法比较具有较明显的优势。

This paper establishes a hardware-software co-verification solution for embedded systems,which is based on fast prototyping FPGA and Instruction Set Simulator（ ISS ）.For this method of achieving,analysis of the co-verification process of interactive software and hardware technology,and gives Bus Functional Model（BFM） structure and method.As an example of that the co-verification solution based on FPGA and ISS takes a clear advantage compared with several other commonly used verification system for embedded applications.