一种时钟恢复算法的FPGA实现

FPGA-based Implementation of Timing Recover Algorithm

给出一种基于全数字接收机的加德纳时钟恢复算法的FPGA实现方法。首先分析了该算法的系统结构及论述各个模块的作用,然后简要给出每个模块的硬件实现方法,其次用MATLAB对该算法进行仿真并给出仿真结果,结果表明该算法是可行的,最后在ISE9.1环境下编写VerilogHDL代码和测试激励,用ModelSim对该算法进行硬件仿真验证。结果表明这种算法时钟抖动小,同步时间快,定时精度高,硬件实现比较简单。该成果已经成功运用在某项目中。

A FPGA-based implementation of Gardner timing recover algorithm in all-digital receiver is proposed. This paper first analyzes the system structure of the algorithm and discusses the role of each module, then briefly describes the hardware implementation of each module, including the algorithm simulation and simulation results with MATLAB, the results show that the algorithm is feasible practicable. Finally, Verilog HDL code is written and test incentive is done in ISE9.1 environment. Hardware simulation of the algorithm indicates that this algorithm is small in clock jitter, fast in synchronization time, precise in timing relatively simple in hardware implementation. Now the research result is successfully applied in certain project.