超高频RFID标签数字基带处理器的设计

Design of a Digital Baseband Processor for UHF RFID Tags

针对超高频RFID标签芯片小面积、低功耗的要求,设计了一种符合EPC C1G2标准的数字基带处理器.在分析其功能基础上进行模块划分,提出了一种新的体系结构;论述并推导了标签工作所需的最低频率;设计了功耗管理模块,在降低功耗的同时,通过调度各个模块,使其正确地协同工作;采用流水线方式进行编码输出;简化了存储器接口的设计.仿真结果符合标准要求,综合后电路规模约7 200门.该电路可应用于超高频RFID标签.

Aiming at the request of low power and .small area of UHF RFID tags, this paper presents a baseband processor, which is compatible with the ＂EPCTM Class-1 Generation-2 UHF RFID Protocol＂. The method of module division and a new architecture are proposed based on the analysis of the tag＇s function. The lowest frequency that a tag needs is discussed and computed. A power management module is designed for both power reduction and scheduling modules in order to make them work in a correct way. The pipelining way of encoding the outputs is adopted. This paper also designs a simplified memory interface. The result of simulation accords with the protocol, and the design has been synthesized, whose area is about 7 200 gates. The circuit can be applied to a UHF RFID tag.