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Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process 被引量:2

Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process
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摘要 Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q;random walk NMOS current source layout routing method,a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-μm CMOS process.The total consumption is only 10 mW from a single 1.2-V power supply,and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively.When the output signal frequency is 1-5 MHz at 100-MSPS sampling rate,the SFDR is measured to be 70 dB.The die area is about 0.2 mm;. Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q^2 random walk NMOS current source layout routing method,a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-μm CMOS process.The total consumption is only 10 mW from a single 1.2-V power supply,and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively.When the output signal frequency is 1-5 MHz at 100-MSPS sampling rate,the SFDR is measured to be 70 dB.The die area is about 0.2 mm^2.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第9期99-103,共5页 半导体学报(英文版)
关键词 current-steering digital-to-analog converter low power matching error current source array mixedsignal integrated circuits current-steering digital-to-analog converter low power matching error current source array mixedsignal integrated circuits
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  • 1Chan K L, Galton I. A 14 b 100 MS/s DAC with fully segmented dynamic element matching. IEEE International Solid State Circuits Conference, 2006:2390.
  • 2Lee D H, Kuo T H, Wen K L. Low-cost 14-bit current-steering DAC with a randomized thermometer-coding method. IEEE Trans Circuits Syst II: Express Briefs, 2009, 56(2): 137.
  • 3Marques A, Bastos J, van den Bosch A, et al. A 12-bit accuracy 300 MS/s update rate CMOS DAC. Proe IEEE International Solid State Circuits Conference, Feb 1998:216.
  • 4Van den Bosch A, Borremans M, Steyaert M, et al. A 10-bit 1- GSample/s Nyquist current-steering CMOS D/A converter. IEEE J Solid-State Circuits, 2001, 36(2): 315.
  • 5Van den Bosch A, Steyaert M, Sansen W. An accurate statistical yield model for CMOS current-steering D/A converters. Proc EEE Int Symp Circuits and Systems (ISCAS), 2000, 4:105.
  • 6Pelgrom M J M, Duinmaijer A C J, Welbers A P G. Matching properties of MOS transistors. IEEE J Solid-State Circuits, 1989, 24:1433.
  • 7Van der Plas G A M, Vandenbussche J, Sansen W, et al. A 14-bit intrinsic accuracy Q2 random walk CMOS DAC. IEEE J Solid- State Circuits, 1999, 34(12): 1709.
  • 8Razavi B. Principle of data conversion system design. Piscataway, NJ: IEEE Press, 1995:148.
  • 9Van den Bosch A, Borremans M, Vandenbussche J, et al. A 12-bit 200-MHz low-glitch CMOS D/A converter. IEEE Custom Integrated Circuits Conf (CICC), 1998:249.
  • 10Malcovati P, Maloberti F, Fiocchi C, et al. Curvature-compensated BiCMOS bandgap with 1-V supply voltage. IEEE J Solid-State Circuits, 2001, 36(7): 1076.

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