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有序统计恒虚警定点数排序的硬件实现 被引量:1

Hardware Implementation of OS-CFAR Fixed-Point Array Sorting Algorithm
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摘要 针对有序统计恒虚警硬件实现中的定点数排序问题,提出一种架构,将排序算法分解,并映射为比较、选择两级硬件阵列,每一级硬件阵列都由基本的比较单元和选择单元组成。针对硬件实现的特点,对比较操作加以简化。利用定点数补码表示正值最高位为0、负值最高位为1的特点,将待比较的两个数值相减,取其差值的最高位作为两个待比较数值大小关系的标志。当一个数值与其所在序列的其他所有值比较之后,就得到一个标志序列,当该数值小于其所在序列中其他一个数值时,标志序列中就有一位为1,则将标志序列累加,所得的值就是该数值在序列中应排的序号。 This paper proposes a kind of hardware architecture to realize the OS-CFAR sorting.Sorting algorithm can be mapped into two hardware arrays with one for comparing and another for selecting,which are respectively composed of comparing cells and selecting cells.The comparing cells are specially simplified for hardware implementation.Since the MSB is either 0 for a positive 2's complement value or 1 for a negative value,so we can use the MSB of any two value's arithmetic difference as a compare flag.By this means we can get a compare flag sequence after comparing a chosen value with the others in the same sequence.If this chosen value is less than another,comparing will produce a "1" in the compare flag sequence and the sum of all the "1's" in this compare flag sequence can be regard as the sequence number of this chosen value.
出处 《雷达科学与技术》 2010年第6期559-562,567,共5页 Radar Science and Technology
关键词 有序统计恒虚警 定点数序列 排序 硬件架构 order statistic CFAR(OS-CFAR) fix-point array sorting hardware architecture
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