摘要
本文分析锁相环（PLL）频率合成器的基本原理，并简单地介绍了ADI公司的集成锁相环芯片ADF4108的结构和性能。然后基于ADF4108芯片设计出一种频率合成器的方案，在该方案中，包含了环路滤波器的设计。通过ADIsimPLL3．1软件仿真，结果显示其相位噪声到达-99．27dBc@10kHz，并且系统工作稳定。
This paper analyses the basic principle of phase-locked loop （PLL）frequency synthesizer. And the internal structure and performance of the integrated PLL chip ADF4108 is described simply. Then, a scheme of PLL frequency synthesizer based on ADF4108 is given. In this scheme, the design of loop filter and VCO is included. The frequency synthesizer is simulated by the ADIsimPLL3.1 software, the simulation result shows that the phase noise of the frequency synthesizer can reach -99.27dBc@ 10 kHz and the system works stably.
出处
《自动化信息》
2011年第1期46-47,58,共3页
Automation Information
关键词
锁相环
环路滤波器
压控振荡器
相位噪声
Phase-locked Loop
Loop Filter
Voltage-controlled Oscillator
Phase Noise
