基于VMM方法学的系统级软硬件协同仿真验证

VMM-based system-level software and hardware co-simulation verification

针对一款高性能复杂SoC芯片的设计,提出了一种新的软硬件协同仿真验证方案。通过比较仿真环境中软硬件间通信的各种实现方式,构建了一种新的符合VMM标准的验证平台。同时为加快覆盖率的收敛速度,给出了随机激励约束的优化方法。实践表明,新的约束和仿真方式使覆盖率收敛速度提高数倍,验证效率显著提高。

To aim at a high-performance complex SoC chip design,the paper proposes a new hardware and software co-simulation verification.By comparing various hardware and software communication implementations for the simulation environment,a new platform to meet the VMM verification standards was built.At the same time to speed up the convergence rate,the optimization method for random constraints was given.Practice showed that with the new constraints simulation approach the convergence rate was increased by several times and the new scheme significantly improved the verification efficiency.