摘要
Planarization used in a gate-last CMOS device was successfully developed by particular technologies of SOG two-step plasma etch-back plus one special etch-back step for SOG/SiO_2 interface trimming.The within-the-wafer ILD thickness non-uniformity can reach 4.19%with a wafer edge exclusion of 5 mm.SEM results indicated that there was little＂dish effect＂on the 0.4μm gate-stack structure and finally achieved a good planarization profile on the whole substrate.The technology provided a CMP-less process basis for sub-100 nm high-k/metal gate-last CMOS integration.
Planarization used in a gate-last CMOS device was successfully developed by particular technologies of SOG two-step plasma etch-back plus one special etch-back step for SOG/SiO_2 interface trimming.The within-the-wafer ILD thickness non-uniformity can reach 4.19%with a wafer edge exclusion of 5 mm.SEM results indicated that there was little＂dish effect＂on the 0.4μm gate-stack structure and finally achieved a good planarization profile on the whole substrate.The technology provided a CMP-less process basis for sub-100 nm high-k/metal gate-last CMOS integration.
基金
Project supported by the Chinese National Science and Technology Major Project(No.2009ZX02035)
the Special Funds for Major State Basic Research Projects,China(No.2006CB302704)
the Opening Project of Key Laboratory of Microelectronics Devices of Integrated Technology(IMECAS)
