基于DHS-NPDS的低功耗运动估计硬件结构设计

Architecture design of low-power motion estimation based on DHS-NPDS for H.264/AVC

为了达到实时视频编码的低功耗、低带宽、省资源3个要求,文中基于改进的归一化部分失真搜索算法,提出一种新颖的运动估计硬件结构.新结构同时支持归一化部分失真搜索和自适应搜索区域调整.前者可降低运动估计的计算复杂度,从而实现低功耗省资源两个要求,后者能避免不必要的外存访问,从而降低数据带宽.在UMC 90 nm CMOS工艺下实现结果表明,相比于传统结构的最好结果,文中结构以6.2%的吞吐率损失,换取面积效率和功耗效率分别提高425.5%和397.5%.

A novel architecture of motion estimation（ME） based on improved normalized partial distortion search is proposed to meet three primary requirements for real-time video encoding,which are low-power,lowbandwidth and high area utilization efficiency.The ME engine supports both normalized partial distortion search and adaptive search window adjustment.The former can reduce the computational complexity of ME to save power and area;the latter can avoid unnecessary accessing the external memory to lower the data bandwidth.The proposed engine has been implemented with UMC 90nm CMOS technology.The implementation results show that,compared with traditional engines,the engine can achieve significant improvements of the hardware efficiency and the power efficiency respectively with a little throughput compromise.