摘要
时钟数据恢复与解复用电路是串行通信系统中接收端的关键电路,其性能的优劣直接影响了整个系统的功能。本文改进了传统的双环时钟数据恢复电路,提出了一种基于空间过采样、时钟数据恢复与串并转换同步完成的双环结构并应用于BLVDS总线控制原型系统中,该原型系统经380项测试,在节点数为5个、收发距离最长为131 m、通信速率达20 MHz时电路工作稳定,同步时间小于10-6 s,误码率低于10-9。
CDR（ Clock and Data Recovery） and SerDes （Serializer/Deserializer） circuit is a critical circuit in the receiver of serial-data transceiver systems, and its performance affects the entire system＇s function di- rectly. This paper presented an improved scheme of the traditional dual-loop clock and data recovery circuit, which was based on special oversampling and in this scheme, the CDR and SerDes could be accomplished simuhaneously. The proposed circuit was applied in a prototype system of BLVDS controlling, which consis- ted of 5 nodes, with the longest distance of 131 meters, and speed of up to 20MHz, and through 380 tests. The circuit can work reliably, with lock time less than 10-6 s, and error rate lower than 10-9.
出处
《微电机》
北大核心
2012年第4期67-69,共3页
Micromotors
基金
陕西省教育厅资助项目(2011JK0927)
