SOI专用集成电路的静态电流监测和失效分析

Failure Analysis of SOI ASIC Based on Quiescent Power Supply Current Test

静态电流测试是一种高灵敏度、低成本的集成电路失效分析技术,在集成电路故障检测、可靠性测试及筛选中的应用日益普遍。针对某绝缘体上硅专用集成电路在老炼和热冲击实验后出现的静态电流测试失效现象,结合样品伏安特性、光发射显微镜和扫描电子显微镜等电学和物理失效分析手段,确定了栅氧化层中物理缺陷的存在、位置及类型;结合栅氧化层经时介质击穿原理分析,揭示了样品的主要失效机理,并分析了经时介质击穿失效的根源,为改进工艺、提高电路可靠性提供了依据。

Quiescent power supply current （/DDQ） test is a sensitive and low cost integrated circuit （IC） failure analysis technology, which has more and more applications in IC fault detec- tion, reliability test and screening. By analyzing the IDDQ failure phenomena in some silicon-on-in- sulator （SOI） application-specific integrated circuit （ASIC） chips accepted aging and thermal shock tests, the existence, locations and types of physical defects in the gate oxide layer are de- termined by combining electrical and physical failure analysis tools such as I-V characteristics, e- mission microscopy （EMMI） and scanning electron microscopy （SEM）. The failure mechanism and the failure sources, are then investigated by analyzing the principle of the time dependent di- electric breakdown （TDDB） of gate oxide layer. The results can provide helpful reference to im- prove the process technolo~：y and reliability of the SOI ASIC chios.