摘要
从小柳光正教授1978年堆叠的两只MOS电容DRAM的三维结构出发,到2010年半导体业界提出了Cu-TSV工艺方法,演进出一部三维集成微纳电子学。本文梳理近6年内的3D-IC测试的一次文献,重点分析了键合前测试、键合中测试和键合后测试。尝试从不同的角度,例如内建自测试、探头技术、串扰、短路与开路检测,以及基于成本优化的温升与应力检测,讨论3D-IC测试所遇到的难题及其解决方法。未来的3D-IC测试技术看好小组数超微探针技术、DfX技术和自适应测试,测试的优化方向必将考虑"成本与功耗折中权重下的良率"新模型。
Starting with the first three-dimensional integration structure of stacked MOS capacitor DRAM invented by Profssor Koyanagi at Tohoku University in 1978, breaking through Cu-Through Silicon Via in 2010 at IBM, 3D-Micro- and Nano-Electronics has been enhanced suiting for mass product semiconductor industry. This work reviews near six years＇ original literatures of 3D-IC test with high light upon pre-, mid-, post-bonding-test on 3D-IC. The encounterd puzzling problems and expecting solutions are discussed in factors such as BIST, probing, cross talking, short and turnoff effect and cost-based optimization in temperature and stress limits. For the future there are alternate techs like mini-group ultra-micro-probes, design for test/debug/yield, and adaptive test that changes test in conditions, flow, contents and limits based on process- and statistical data analyses. The optical direction of 3D-IC test will face novel yield model accounting for trade-off of test-cost and test-power-consumption.
出处
《中国集成电路》
2013年第10期63-69,86,共8页
China lntegrated Circuit
基金
2012年苏州大学国家自然科学基金启动项目
