摘要
结合Buck型DC-DC转换器的工作原理,从系统的稳定性和响应速度要求出发,提出一种高性能误差放大器及环路补偿方案。该误差放大器具有高的共模抑制CMRR和高的电源抑制比PSRR。电路结构采用CSMC 0.5μm BCD工艺,仿真结果表明,该误差放大器共模抑制比为106 dB,电源抑制比为129 dB,其性能良好,满足DC-DC转换器的系统需要。
A high performance error-amplifier circuit,which meets the requirements of loop stability and response speed of DC-DC converter,is presented in this paper.And based on it,a loop compensation is presented.The proposed error-amplifier circuit achieves high common mode rejection ratio as well as power supply rejection ratio.The error-amplifier is designed and implemented by CSMC 0.5 μm BCD process.The simulation results show that the common mode rejection ratio is 106 dB and the power supply rejection ratio is 129 dB,which proves a good performance and can meet the needs of DC-DC converter system.
出处
《电子技术应用》
北大核心
2014年第10期43-45,共3页
Application of Electronic Technique
