应用于高性能处理器的并行接口IP核的设计与验证

Design and verification of Parallel Interface IP Core Used in High-performance Processor

本文采用自顶向下的Top-Down设计方法,详细描述了并行接口的设计与验证,包括接口的定义、模块的划分、模块设计、接口验证,并给出了设计过程中的部分RTL代码和仿真波形,此款并行接口IP核已成功应用于高性能处理器芯片,具有实际的工程意义。

According to Top-Down design theory, the thesis described the design and verification of the parallel interface, including the defined of input and output signals, the divided of the modules, the design of the modules and the verification of the interface. It also presented the partial RTL coding and simulation waveform during design. Presently, the parallel interface had been applied in the high performance processor chip, showing the validity in the enginerring application.