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Tunnel junctions in a III-V nanowire by surface engineering 被引量:1

Tunnel junctions in a III-V nanowire by surface engineering
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摘要 We demonstrate a simple way of fabricating high performance tunnel devices from p-doped InAs nanowires by tailoring the n-doped surface accumulation layer inherent to InAs surfaces. By using appropriate ammonium sulfide based surface passivation before metallization without any further thermal treatment, we demonstrate characteristics of tunnel p-n junctions, namely Esaki and backward diodes, with figures of merit better than previously published for InAs homojunctions. The further optimization of both the surface doping, in a quantitative way, and the device geometry allows us to demonstrate that these nanowire-based technologically-simple diodes have promising direct current characteristics for integrated high frequency detection or generation.
出处 《Nano Research》 SCIE EI CAS CSCD 2015年第3期980-989,共10页 纳米研究(英文版)
关键词 semiconductor nanowire tunnel junction indium arsenidecompounds DOPING Ⅲ-Ⅴ semiconductors 表面工程 纳米线 隧道结 InAs 隧道设备 表面钝化 表面掺杂 几何形状
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