期刊文献+

一种基于GPU的高精度体系结构级功耗模型 被引量:2

High-precision Architecture-level Power Model Based on GPU
下载PDF
导出
摘要 随着硬件功能的不断丰富和软件开发环境的逐渐成熟,GPU开始被应用于通用计算领域,协助CPU加速程序运行。为了追求高性能,GPU往往包含成百上千个核心运算单元,高密度的计算资源使得其性能远高于CPU的同时功耗也高于CPU,功耗问题已经成为制约GPU发展的重要问题之一。在深入研究Fermi GPU架构的基础上,提出一种高精度的体系结构级功耗模型,该模型首先计算不同native指令及每次访问存储器消耗的功耗;然后根据应用在硬件上的执行指令和采样工具获得采样结果,分析预测其功耗;最后通过13个基准测试应用对实际测试与功耗模型测试结果进行对比分析,该模型的预测精度可达90%左右。 As hardware functions are constantly developing,and software development environments gradually mature,the graphics processing unit(GPU)has been applied to general purpose computation to help the central processing unit(CPU)accelerate a program.To obtain high performance,a GPU generally contain hundreds of core arithmetic units.Owing to the existence of high-density computing resources,the performance of the GPU is much superior to that of the CPU,while its power consumption is larger than that of the CPU.Power consumption has become one of the important issues restricting the development of GPU.Based on the study of the Fermi GPU architecture,a high-precision architecture-level power model was proposed in this research.In this model,the power consumed by different native instructions,and each memory access,were first calculated,then the power consumption was analysed and predicted according to the execution instructions as applied to the hardware,and the sampling results were acquired using sampling instruments.Finally,the results obtained from practical testing and the power model were compared by using 13 benchmark applications.It is demonstrated that the prediction accuracy of the model can reach approximately 90%.
出处 《计算机科学》 CSCD 北大核心 2016年第11期30-35,共6页 Computer Science
基金 国家自然科学基金(61300029 61672168)资助
关键词 GPU FERMI 功耗模型 native指令 存储器功耗 GPU Fermi Power model Native instruction Memory power consumption
  • 相关文献

参考文献2

二级参考文献37

  • 1骆祖莹.芯片功耗与工艺参数变化:下一代集成电路设计的两大挑战[J].计算机学报,2007,30(7):1054-1063. 被引量:17
  • 2http://ati, amd. com/technology/streamcomputing/product_ FireStream_9250. html.
  • 3Luebke D, Harris M, Govindaraju N, Lelohn A, HoustonM, Owens J, Segal M, Papakipos M, Buck I. GPGPU General-purpose computation on graphics hardware//Pro ceedings of the 2006 ACM/IEEE Conference on Supercom puting(SC'06). Tampa, Florida, 2006.
  • 4Fan Xiaobo, Ellis Carla S, Lebeck Alvin R. The synergy be-tween power aware memory systems and processor voltage scaling//Proceedings of the Workshop on Power-AwareComputer Systems ( PACS-03 ). New York, NY, USA, 2003: 164-179.
  • 5Hong S, Kim H. An analytical model for a GPU architecturewith memory-level and thread-level parallelism awareness// Proceedings of the 36th Annual International Symposium onComputer Architecture (ISCA'09). Austin, TX, USA, 2009:152-163.
  • 6NVIDIA Corporation. CUDA Programming Guide, Version 2.1.
  • 7Burd T, Brodersen R. Design issues for dynamic voltagescaling//Proceedings of the 2000 International Symposium on Low Power Electronics and Design (ISLPED' 00). Rapallo, Italy, 2000:9-14.
  • 8Bakhoda Ali, Yuan George, Fung Wilson W L, Wong Henry, Aamodt "For M. Analyzing CUDA workloads using adetailed GPU simulator//Proceedings of the IEEE Interna tional Symposium on Performance Analysis of Systems and Software (ISPASS). Boston, MA, 2009:163-174.
  • 9Brooks D, Tiwari V, Martonosi M. Wattch: A framework for architectural-level power analysis and optimizations//Proceedings of lhe 271h International Symposium on Computer Architecture ( ISCA ). Vancouver, British Columbia, Canada, 2000; 83-94.
  • 10Ramani K, Ibrahim A, Shimizu D. PowerRed.- A flexible modeling framework for power efficiency exploration inGPUs//Proceedings of the Workshop on General Purpose Processing on Graphics Processing Units. New York, NY, USA, 2007:185-192.

共引文献12

同被引文献14

引证文献2

二级引证文献8

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部