2Keating M, Flynn D, Aitken R,et al. Low power Methodology Manual for System-on-Chip Design [M]. NewYork: Springer, 2007: 34-38.
3Emnett F, Biegel M. Power Reduction Through RTL Clock Gating [R]. SNUG Conference, San Jose, 1999.
4Mehra R, Rabaey J. Behavioral Level Power Estimation and Exploration. In Proc. Int. Workshop Low Power Design, Napa Valley, CA, Apr. 1994, Piscataway, N J, IEEE press 1994:197-202.
5Rabaey J M. Low Power Design Essentials [M]. NewYork: Springer, 2009:55-58.
6Najm F. Towards a high-level power estimation capability. 1995 Int Syrup on Low Power Design, 1995, 87-92.
7拉扎维.模拟CMOS集成电路设计[M].陈贵灿,译.西安:西安交通大学出版社,2003.
8ALLEN P E,HOLBERG D R.CMOS模拟集成电路设计,(第3版)[M].冯军,李智群,译.北京:电子工业出版社,2005.
9BAKER R J.CMOS电路设计、布局、仿真(第2版)[M].刘艳艳,张为,译.北京:人民邮电出版社,2008.
10ENZ C C,KRUMMENACHER F,VITTOZ E A.An analytical MOS transistor model valid in All regions of operation and dedicated to low-voltage and low-current applications[J].analog Integrated circuits and Signal Processing,1995,8(1),83-114.