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TSV阵列的串扰耦合与布局结构分析

Crosstalk coupling and layout analysis of TSV array
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摘要 针对高密度TSV阵列中相邻TSV受耦合电容影响产生耦合噪声,使信号传输可靠性下降,基于TSV阵列,分析了TSV数量和位置变化对串扰耦合的影响。以3×3 TSV阵列为研究对象,提出了4种布局结构并进行仿真分析。实验结果表明:TSV阵列中的耦合电容不会随着数量的增加而线性增加,边缘相邻TSV间的耦合电容比中间相邻TSV间的耦合电容大40%;根据串扰耦合得到2种利于TSV阵列扩展的结构模型,其具有较好的传输性能。 In high density TSV array, the adjacent TSV is affected by coupling capacitance to produce coupling noise, which reduces the reliability of signal transmission. Based on the TSV array, the influence of the number and location of TSV on crosstalk coupling is analyzed. Then, taking 3×3 TSV array as the research object, four layout structures are proposed and simulated. The experimental results show that the coupling capacitance of the TSV array will not increase linearly with the increase of the number. The coupling capacitance between adjacent TSVs at the edge is about 40% larger than that between adjacent TSVs in the middle. According to crosstalk coupling, two structural models are obtained, which are favorable for TSV array expansion and have better transmission performance.
作者 陈熠 尚玉玲 CHEN Yi;SHANG Yuling(School of Electronic Engineering and Automation,Guilin University of Electronic Technology,Guilin 541004,China)
出处 《桂林电子科技大学学报》 2020年第2期125-129,共5页 Journal of Guilin University of Electronic Technology
基金 国家自然科学基金(61661013) 广西自然科学基金(2018GXNSFAA281327)。
关键词 TSV阵列 耦合电容 布局结构 TSV array coupling capacitance layout structure
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  • 1Meindl J D, Chen Q, Davis J A. Limits on silicon nanoelectronics for terascale integration[J]. Science, 2001, 293(5537) : 2044-2049.
  • 2Thorolfsson T, Gonsalves K, Franzon P D. Design automation for a 3DIC FFT processor for synthetic ap erture radar: A case study[C]// Design Automation Conference46th ACM/IEEE. San Francisco, CA:IEEE, 2009 : 51-56.
  • 3Pang C, Wang Z, Ren X, et al. Electrical simulation of 3X3 TSV array with different signal and ground patterns [ C ]// Electronic Packaging Technology (ICEPT), 2013 14th International Conference on.Dalian. IEEE, 2013:417-420.
  • 4Yao W, Shi F, He L, et al. Power-bandwidth trade off on TSV array in 3D IC and TSV-RDL junction de sign challenges[C]// Electrical Performance of Elec- tronic Packaging and Systems (EPEPS), 2012 IEEE 21st Conference on. Tempe, AZ: IEEE, 2012 : 79-82.
  • 5Zhao Y, Khursheed S, A1-Hashimi B M. Cost-effec- tive TSV grouping for yield improvement of 3D-ICs [C]//2012 IEEE 21st Asian Test Symposium IEEE. New Delhi: IEEE, 2011 : 201-206.
  • 6朱健.3D堆叠技术及TSV技术[J].固体电子学研究与进展,2012,32(1):73-77. 被引量:19
  • 7王伟,林卓伟,陈田,刘军,方芳,吴玺.功耗约束下的3D多核芯片芯核级测试调度算法[J].电子测量与仪器学报,2012,26(7):591-596. 被引量:11
  • 8余乐,杨海钢,谢元禄,张甲,张春红,韦援丰.三维集成电路中硅通孔缺陷建模及自测试/修复方法研究[J].电子与信息学报,2012,34(9):2247-2253. 被引量:6
  • 9王敏,王友仁,张砦,孔德明.三维结构可重构阵列在线自诊断与容错方法[J].仪器仪表学报,2013,34(3):650-656. 被引量:11
  • 10宋佳佳,李文石.三维集成电路测试进展[J].中国集成电路,2013,22(10):63-69. 被引量:3

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