基于V93000的FPGA测试优化方法研究

Research on FPGA Test Optimization Method Based on 93000

基于Xilinx公司的现场可编程门阵列FPGA XC6VLX240T-2FF1156I,JTAG端口配置烧写时间远大于测试时间,并且搭建实装测试平台不适合大批量生产的需求,不能满足此类产品的测试发展需求,该文提出了一种FPGA测试时间优化方法;采用Advantest公司的V93000测试机,通过在周期内加载2行配置向量对电路配置比特流的测试时间进行优化,删减芯片配置初始化源码,从而减少测试时间,同时该文也将结合Xilinx公司提供的源码和IP核进行模型仿真生成测试码,提高FPGA芯片测试覆盖率,实验证明此方法大大提高了在线配置的速度,对提高测试效率具有一定的参考价值。

Based on Xilinx's Field Programmable Gate Array FPGA XC6VLX240T-2FF1156I,the JTAG port configuration programming time is much longer than the test time,and the build test platform is not suitable for mass production and cannot meet the test development needs of such products.This article A method for optimizing FPGA test time is proposed;Advantest's V93000 test machine is used to optimize the test time of the circuit configuration bit stream by loading 2 rows of configuration vectors in the cycle,and the chip configuration initialization source code is deleted to reduce the test time.At the same time,this article will also use the source code and IP core provided by Xilinx to perform model simulation to generate test codes to improve FPGA chip test coverage.The test shows that this method greatly improves the speed of online configuration and has certain reference value for improving test efficiency.