深亚微米SOI工艺ESD防护器件设计

ESD Protection Device Design Based on Deep Submicron SOI Technology

在集成电路设计领域,绝缘体上硅(SOI)工艺以其较小的寄生效应、更快的速度,得到广泛应用。但由于SOI工艺器件的结构特点及自加热效应(SHE)的影响,其静电放电(ESD)防护器件设计成为一大技术难点。当工艺进入深亚微米技术节点,基于部分耗尽型SOI(PD-SOI)工艺的ESD防护器件设计尤为困难。为了提高深亚微米SOI工艺电路的可靠性,开展了分析研究。结合SOI工艺器件的结构特点,针对性地进行了ESD防护器件选择,合理设计了器件尺寸参数,并优化设计了器件版图。使用该设计的一款数字电路,通过了4.5 k V人体模型(HBM)的ESD测试。该设计有效解决了深亚微米SOI工艺ESD防护器件稳健性弱的问题。

In the field of the integrated circuit design,the silicon on insulator(SOI)technology is used widely for the great advantage of less parasitic effects and faster speed.But the electro static discharge(ESD)protection device design becomes a big technical difficulty for the device’s structure feature and self-heating effects(SHE)of the SOI technology.When reaching the deep submicron technology node,the ESD protection device design becomes more difficult based on partially depleted SOI(PD-SOI)technology.A research was developed for improving the reliability of the deep submicron SOI technology.Associating with the device’s structure feature of the SOI technology,an ESD protection device was targeted,the device’s size and parameters were finalized,and the layout was designed optimally.A digital circuit has passed the human body model(HBM)ESD test above 4.5 k V by using this design.The problem is solved efficiently of the weak robustness about the ESD protection device based on deep submicron SOI technology.