一种10位高速Pipeline-SAR混合型ADC设计

Design of a 10-bit High Speed Pipeline-SAR Hybrid ADC

基于180 nm CMOS工艺,设计了一种无残差放大的10位100 MS/s流水线与逐次逼近混合型ADC。采用两级流水线-逐次逼近混合型结构,第一级完成4位粗量化转换,第二级完成6位细量化转换。为了降低整体电路功耗,采用单调式电容控制切换方式,两级之间残差电压采用采样开关电荷共享方式实现。采用异步时序控制逻辑,进一步提升了能量利用率和转换速度。后仿真结果表明,在100 MS/s奈奎斯特采样率下,有效位数为9.39 bit,信噪失真比为58.34 dB,1.8 V电源电压下整体功耗为5.9 mW。

A 10-bit 100 MS/s pipeline-SAR hybrid ADC without residue amplifier was designed in a 180 nm CMOS process.A two-stage pipeline-SAR hybrid structure was adopted,with the 4-bit most significant bit(MSB)conversion completed in the first stage and the 6-bit least significant bit(LSB)conversion completed in the second stage.In order to reduce the power consumption,the monotonic switching procedure was used,and the residue voltage was delivered from the first stage to the second one by charge sharing.The asynchronous timing control logic was applied to further improve the energy efficiency and the conversion speed.The post-layout simulation results showed that this ADC achieved an ENOB of 9.39 bit and a SNDR of 58.34 dB at 100 MS/s Nyquist sampling rate.The power consumption was 5.9 mW with a 1.8 V supply voltage.