面向寄存器传输级设计阶段的高效高精度功耗预测模型

An Efficient and High-precision Power Consumption Prediction Model for the Register Transfer Level Design Phase

功耗已成为电路设计的关键性能目标之一,现有商业工具PrimeTime PX(PTPX)的功耗预精度高,但是运行时间长,且仅面向已经生成网表的逻辑综合或者物理实现阶段。因此,降低功耗分析时间,且前移功耗预测在芯片设计中的环节变得尤为重要。该文提出一种面向千万门级专用集成电路(ASIC)的寄存器传输级(RTL)功耗预估方法,可在RTL设计阶段实现快速且准确的周期级功耗预测:根据输入信号的功耗相关性原则使用基于平滑截断绝对偏差惩罚项(SCAD)的嵌入法对输入信号自动筛选,从而解决大信号特征输入数量对预估性能的影响;通过时序对准方法对仿真波形数据进行校正,解决了sign-off级功耗与RTL级仿真波形之间的时序偏差问题,有效提升了模型预测的精度;建立了仅拥有两个卷积层和1个全连接层的浅层卷积神经网络模型,学习相邻位置和相邻时间上的信号活动与功耗的相关性信息,充分降低部署开销,使训练速度得到显著提高。该文使用开源数据集、28 nm工艺节点的3×10^(7)门级工业级芯片电路作为测试对象,实验结果表明,功耗预测结果和物理设计后PTPX分析结果相比,平均绝对百分比误差(MAPE)小于1.71%,11k时钟周期的功耗曲线预测耗时不到1.2 s。在场景交叉验证实验中,模型的预测误差小于4.5%。

Power consumption is identified as a critical performance objective in circuit design.Existing power estimation tools,such as PrimeTime PX(PTPX),provide high accuracy but are hampered by lengthy execution times and are confined to logic synthesis or physical implementation stages with an already generated netlist.As a result,the need to reduce power analysis time and stress the importance of forward power prediction in chip design has been recognized.A power estimation model for early-stage large-scale Application Specific Integrated Circuit(ASIC)is introduced,which can achieve fast and accurate cycle-level power prediction at the Register Transfer Level(RTL)design stage.The model applies the Smoothly Clipped Absolute Deviation(SCAD)embedding method based on the power correlation principle of input signals for automatic signal selection,addressing the impact of large input feature numbers on estimation performance.A timing alignment method is employed to correct the timing deviation between sign-off level power and RTL-level simulation waveform,enhancing prediction accuracy.The strong nonlinearity of a shallow two-layer convolutional neural network is utilized by the model for power training,consisting of two convolutional layers and one fully connected layer,which reduces computational overhead.Power labels use backend Sign-off level power output data to enhance the accuracy of prediction results.This power estimation model is evaluated on a 28 nm Network Processor(NP)with more than 30 million gates.Experimental results demonstrate that the Mean Absolute Percentage Error(MAPE)of this model for predicting total circuit power consumption is less than 1.71%when compared with the PTPX analysis results following physical design back-annotation.The model takes less than 1.2 s to predict the power curve for 11k clock cycles.In cross-validation experiments with different scenarios,the prediction error of the model is found to be less than 4.5%.