期刊文献+

CMOS电路最大功耗宏模型 被引量:1

Macro Model for Estimating Maximum Power of CMOS Circuits
下载PDF
导出
摘要 参照已有的平均功耗宏模型研究成果 ,将电路最大功耗假设为输入向量对序列长度与跳变率的函数 ,并采用神经元网络拟合出该函数 ISCAS85电路集的实验结果表明 ,最大功耗宏模型的计算结果与门级电路最大功耗的实际模拟结果之间的误差可以控制在 10 Based on the achievements of macro model for mean power of register transfer level (RTL) circuits, this paper models maximum power of circuits as a function of the pattern pair sequence length and transition density, then uses neural networks to fit the maximum power function. Experimental results on ISCAS85 benchmarks demonstrate that the discrepancy between computed values of macro model and simulated results can be limited to 10%.
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2003年第9期1118-1121,共4页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金国际合作项目 ( 60 112 112 0 70 6) 美国国家自然科学基金 (CCR- 0 0 963 83 ) 国家自然科学基金重点项目 ( 90 2 0 70 0 2 ) 国家"八六三"高技术研究发展计划 ( 2 0 0 1AA1110 70 )资助
关键词 CMOS电路 最大功耗宏模型 集成电路 低功耗设计 CMOS VLSI maximum power macro model
  • 引文网络
  • 相关文献

参考文献7

  • 1骆祖莹,闵应骅,杨士元.一种新的CMOS组合电路最大功耗快速模拟方法[J].计算机辅助设计与图形学学报,2001,13(7):577-581. 被引量:2
  • 2Radu Marculescu, Diana Marculescu, Massoud Pedram.Sequence compaction for power estimation: Theory and practice[J]. IEEE Transactions on CAD, 1999, 18(7) : 973--993.
  • 3Enrico Macii, Massoud Padram, Fabio Somenzi. High-level power modeling, estimation, and optimization [A]. In:Proceedings of the 34th ACM/IEEE Design Automation Conference [C]. Anaheim: IEEE Computer Society, 1997.504--511.
  • 4Chela Zhan-ping, Roy Kaushik. A power macro-modeling technology based on power sensitivity [A]. In: Proceedings of the 35th ACM/IEEE Design Automation Conference [C]. San Francisco: IEEE Computer Society, 1998. 678--683.
  • 5Gupta Sudodh, Najm Farid N. Power modeling for high-level power estimation [J]. IEEE Transactions on VLSI, 2000, 8(1): 18--29.
  • 6Zhao Zhuxing, Min Yinghua. The least upper bound of power dissipation in CMOS eireuits [A]. In: Proceedings of the 5th International Conferenee on Computer Aided Design and Computer Graphies [ C]. Shanghai: China Computer Federation, 1997. 506--511.
  • 7Manich S. Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model[A]. In: Proceedings of European Design and Test Conference[C]. Paris: European Design and Test Association, 1997. 597-- 602.

二级参考文献3

  • 1Wang C Y,IEEE Trans VLSI,1998年,6卷,1期,134页
  • 2Qiu Qinru,Proceedings of the 35th ACM/IEEE Design Automation Conference,1998年,684页
  • 3Zhao Zhuxing,Proceedings of the 5th International Conference on CADCG,1997年,506页

共引文献1

同被引文献10

  • 1Oh S Y, Chang K J. 2001 needs for multi-level interconnect technology[J]. IEEE Circuits and Devices, 1995, 11(1): 16~21.
  • 2Frye R C, Chen H Z. Optimal self-damped lossy transmission line interconnect for multichip modules [J]. IEEE Transactions on Circuits Systems Ⅱ, 1992, 39(11): 765~771.
  • 3Zhao M, Panda R, Sapatnekar S, et al. Hierarchical analysis of power distribution network [A]. In: Proceedings of Design Automation Conference, Los Angeles, 2000. 150~ 155.
  • 4Cho D S, Lee K H, Jang G J, et al. Efficient modeling techniques for IR drop analysis in ASIC designs [A]. In:Proceedings of IEEE International ASIC/SOC Conference,Washington D C, 1999. 64~68.
  • 5Hu J L, Chan C H, Sarkar T K. Generation of broadband response for the ground bounce [A]. In: Proceedings of IEEE Conference on Electrical Performance of Electronic Packaging,Scottsdale, 2000. 47~50.
  • 6Lienig J, Jerke G, Adler T. Electromigration avoidance in analog circuits: Two methodologies for current-driven routing [A]. In: Proceedings of Design Automation Conference,Bangalore, 2002. 372~378.
  • 7Mi W, Brews J R. Guidelines governing the need for low impedance drivers for MCM's [J]. IEEE Transactions on Components, Packaging, and Manufacturing Technology,1993, 16(2): 152~156.
  • 8Cappuccino G, Cocorullo G. Time-domain model for power dissipation of CMOS buffers driving lossy lines [J ]. Electronics Letters, 1999, 35(12): 959~960.
  • 9Shin Y, Sakurai T. Power distribution analysis of VLSI interconnects using model order reduction [J]. IEEE Transactions on Computer-Aided Design, 2002, 21 (6): 739~745.
  • 10Heydari Para, Abbaspour Soroush, Pedram Massoud. A comprehensive study of energy dissipation in lossy transmission lines driven by CMOS inverter [A]. In: Proceedings of Custom Integrated Circuits Conference, Orlando, 2002. 517~520.

引证文献1

二级引证文献4

;
使用帮助 返回顶部