单粒子瞬态效应硬件注入模型实现和仿真

A Single Event Transient Fault Injection Model for Emulation

基于量化组合逻辑门延迟思想和扫描测试的方法,提出了一种适用于FPGA硬件模拟单粒子瞬态效应的门级注入模型.该模型考虑了电气掩蔽效应对脉冲传输的影响,通过该模型可以对组合电路任意逻辑门进行错误注入.基于该模型对ISCAS’85基准电路进行单粒子瞬态的研究,实验结果表明该脉冲产生方法高效,注入速度达到105 faults/s.

This paper presents a single event transient injection model for FPGA emulation based on quantization and scan test.A complete fault injection can be implemented with this approach.Experiment results of ISCAS'85benchmark demonstrate that the model can be easily implemented in a FPGA.And the proposed approach could increase SET fault analysis speed to 105 faults/s.