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ASIC Design of High-Speed Low-Power HDLC Controller

ASIC Design of High-Speed Low-Power HDLC Controller
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摘要 Combined with the engineering requirement, a high-speed low-power ASIC design of HDLC controller based on RS-485 bus is given in this paper. On principle of Top-Down design, this ASIC design uses multi-techniques to reduce its die area and dynamic power, and overcomes some problems appeared frequently in application systems of the RS-485 circuits formed by the Standard Interface Chips. This design also improves the system reliability and reduces the system area. Combined with the engineering requirement, a high-speed low-power ASIC design of HDLC controller based on RS-485 bus is given in this paper. On principle of Top-Down design, this ASIC design uses multi-techniques to reduce its die area and dynamic power, and overcomes some problems appeared frequently in application systems of the RS-485 circuits formed by the Standard Interface Chips. This design also improves the system reliability and reduces the system area.
作者 陈禾 韩月秋
出处 《Journal of Beijing Institute of Technology》 EI CAS 2003年第S1期66-69,共4页 北京理工大学学报(英文版)
基金 the Ministerial Level Foundation(1407327)
关键词 HDLC ASIC RS-485 bus communication controller HDLC ASIC RS-485 bus communication controller
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