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A 12bit 300MHz Current-Steering CMOS D/A Converter 被引量：1

12位300MHz电流驱动型DAC(英文)
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摘要 The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz. 在电路误差、电路占用芯片面积相互折中和妥协的前提下提出了一种8+4结构的电流驱动型数模转换器.采用Q2randomwalk方法设计了一个新型的双中心对称的电流矩阵,确保数模转换器的线性度.分析并求出了最佳电平交叉点,设计了电平钳位锁存器对开关电平限幅,DAC动态性能得到改善.在12位分辨率下,刷新率达到300MHz以上.
作者 倪卫宁 耿学阳 石寅
机构地区 中国科学院半导体研究所
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2005年第6期1129-1134,共6页 半导体学报（英文版）
基金 国家高技术研究发展计划资助项目(批准号:2002AA1Z1200)~~
关键词 D/A converter current-steering CMOS mixed integrated circuit cross-point Q2 random walk D/A转换器 电流驱动 CMOS混合集成电路 电平交叉点 Q^2random walk
分类号 TN432 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献9

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二级参考文献15

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共引文献3

同被引文献8

  • 1PELGROM M, DUINMAIJER A, WELBERS A. Matching properties of MOS transistors [J]. IEEE J Sol Sta Circ, 1989, 24(5): 1433-1439.
  • 2BOSCH A V, STEYAERT M, SANSEN W. An accurate statistical yield model for CMOS current-steering D/A converters [C]// Proe IEEE Int Symp Circ Syst. 2000, (2): 105-108.
  • 3CONG Y H, GEIGER R L. Formulation of INL and DNL yield estimation in current-steering D/A converters[C]//Proc IEEE Int Symp Circ and Syst. 2002: 149-152.
  • 4KOSUNEN M, VANKKA J, TEIKARI I, et al. DNL and INL yield models for a current-steering D/A converter[C] // Proc IEEE Int Symp Circ Syst. Thailand. 2003:969-972.
  • 5RADULOV G I, HEGT J A. Brownian-bridge-based statistical analysis of the DAC INL caused by current mismatch[J]. IEEE Circ and Syst, 2007, 54(2): 146-150.
  • 6BARRANCO B L, GOTARREDONA T S. On an efficient CAD implementation of the distance term in Pelgroin's mismatch model [J]. IEEE Comp Aid Des Integr Cite And Syst, 2007, 26(8): 1534-1538.
  • 7CONG Y H, GEIGER R L. Switching sequence optimization for gradient error compensation in thermometer decoded DAC arrays [J]. IEEE Circ and Syst, 2000, 47(7): 585-595.
  • 8江金光,何怡刚,吴杰.12位80MHz采样率具有梯度误差补偿的CMOS电流舵D/A转换器实现[J].Journal of Semiconductors,2003,24(12):1324-1329. 被引量：4

引证文献1

Journal of Semiconductors
2005年 第6期

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