宽带综合数据光同步网节点解串器的研究

Research of WIDOSNet node deserializer

为了保证网络传输的实时性、可靠性,在研究宽带综合数据光同步网络体系结构的基础上,提出了一种基于FPGA的宽带综合数据光同步网节点控制器的硬件结构设计。该系统主要采用FPGA芯片EP2C5T144C6、解串器芯片DS90C124实现数据传输。节点解串器将接收到的数据进行串/并转换后,发送给各个节点数据控制单元。此设计增强了系统的灵活性,提高了网络节点的可靠性,结构简单适应于不同应用领域的需求。

After studying on the architecture of WIDOSNet, this paper puts forward a hardware design of Wideband Integration Data Optical Synchronization Network （WIDOSNet） node deserializer based on FPGA. The system adopts FPGA chip EP2C5T144C6 and deserializer DS90C124. After converting serial data into parallel data, the node deserializer transmits the data to each node data control units. Such design enhances the flexibility of the system and improves the reliability of the network nodes. Its simple structure is also suitable for different applications.