期刊文献+

一种多处理器总线接口部件的验证环境的搭建 被引量:1

Verification Environment Fabrication of Bus Interface Unit in the Multiprocessors
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摘要 设计和验证周期的不断紧缩,给芯片验证工作者带来了很大的挑战;为了提高验证效率,对芯片的验证方法和验证环境的搭建进行了深入地研究;以"龙腾R2"微处理器总线接口部件为例,详细阐述一种面向对象的功能覆盖率反馈以及自检查验证环境的搭建流程;实验表明,改进后的验证环境在验证效率以及功能点覆盖面方面都明显优于改进前的验证环境。 As the cycle of design and verification are shrinking increasingly, chip verification engineers are faced more and more challenge. To improve verification efficiency, the author make a deep research on verification methodology and verification environment fabrication. This paper gives an detailed exPlanation of the verification environment based on the object-oriented functional coverage feedback and selfcheck technique when design the bus interface of the Longtium R2 microprocessor. The experiment shows that the improved verification environment has priority on the verification efficiency and the functional points coverage over the elder verification environment.
出处 《计算机测量与控制》 CSCD 2008年第6期843-845,871,共4页 Computer Measurement &Control
基金 国家自然科学基金(60573107)。
关键词 总线接口部件 总线功能模型 功能覆盖率 自检查 bus interface unit bus functional model functional coverage selfcheck
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参考文献5

  • 1Zhang E. Functional Verification with Completely Self-checking Tests [C]. IEEE1997. 2-10.
  • 2Litterick M. Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments [A]. Proceedings of the fifth International Workshop on Microprocessor Test and Verification [C]. 2004, 75-90.
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二级参考文献3

  • 1Greeg D Lahti, Tim L Wilson. Designing Procedural-Based Behavioral Bus Functional Models for High Performance Verification, SNUG, 1999.
  • 2Synopsys. Inc, PCI/PCI-X FlexModel User's Manual, 2003,5.
  • 3Janick Bergeron. Writing Testbenches-Functional Verification of HDL Models, Boston, Kluwer Academic Publisher,2000.

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