Step memory polynomial predistorter for power amplifiers with memory

用于功率放大器的阶梯记忆多项式预失真器(英文)

To reduce the number of digital predistortion coefficients, a step memory polynomial （SMP）predistorter is presented. The number of predistortion coefficients is decreased by adjusting the maximum nonlinear order for different memory orders in the traditional memory polynomial （MP）predistorter. The proposed SNIP predistorter is identified by an offline learning structure on which the coefficients can be extracted directly from the sampled input and output of a PA. Simulation results show that the SMP predistorter is not tied to a particular PA model and is, therefore, robust. The effectiveness of the SMP predistorter is demonstrated by simulations and experiments on an MP model, a parallel Wiener model, a Wiener-Hammerstein model, a sparsedelay memory polynomial model and a real PA which is fabricated based on the Freescale LDMOSFET MRF21030. Compared with the traditional MP predistorter, the SMP predistorter can reduce the number of coefficients by 60%.

为了减少数字预失真系数的数量,提出了阶梯记忆多项式(SMP)预失真器.该预失真器通过改变传统记忆多项式预失真器中不同记忆深度对应的最大非线性阶数以降低系数数量.SMP预失真器系数的提取采用离线学习结构,直接通过功率放大器(PA)的输入、输出采样数据计算预失真系数.仿真结果表明了SMP预失真器的鲁棒性,它并不局限于某一特定PA模型.SMP预失真器的有效性分别在记忆多项式模型、并行Wiener模型、Wiener-Hammerstein模型、非单位延时记忆多项式模型和基于Freescale LDMOSFET MRF21030制作的实际PA上,通过仿真和实验的方式进行了验证.与传统MP预失真器相比, SMP预失真器可减少系数数量60%以上.