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Design of a 6.25 Gbps backplane SerDes with adaptive decision feedback equalization 被引量:1

Design of a 6.25 Gbps backplane SerDes with adaptive decision feedback equalization
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摘要 A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference (ISI), the core employed a half-rate four-tap decision feedback equalizer (DFE). The equalizer used the Signsign least mean-squared (SS-LMS) algorithm to realize the coefficient adaptation. An automatic gain control (AGC) amplifier with the sign least mean-squared (S-LMS) algorithm has been used to compensate the transmission media loss. To recover the clock signal from the input data serial and provide for the DFE and AGC, a bang-bang clock recovery (BB-CR) is adopted. A third order phase loop loek (PLL) model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioral modeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver. The DFE recovered data over a 34" FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontal eye opening of 0.87 UI, and a vertical eye opening of 500 mVpp. A 6.25 Gbps SerDes core used in the high speed backplane communication receiver has been designedbased on the OIF-CEI-02.0 standard. To counteract the serious Inter-Symbol-Interference (ISI),the core employed a half-rate four-tap decision feedback equalizer (DFE). The equalizer used the Sign-signleast mean-squared (SS-LMS) algorithm to realize the coefficient adaptation. An automatic gain control(AGC) amplifier with the sign least mean-squared (S-LMS) algorithm has been used to compensatethe transmission media loss. To recover the clock signal from the input data serial and provide for theDFE and AGC, a bang-bang clock recovery (BB-CR) is adopted. A third order phase loop lock (PLL)model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioralmodeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver.The DFE recovered data over a 34' FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontaleye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.
出处 《High Technology Letters》 EI CAS 2009年第4期409-415,共7页 高技术通讯(英文版)
基金 Supported by the High Technology Research and Development Programme of China (No. 2003AA31g030).
关键词 Serializer/Desterilizer (SerDes) adaptive equalizer decision feedback equalization (DFE) automatic gain control (AGC) amplifier bang-bang clock recovery (BB-CR) 判决反馈均衡 环境设计 SERDES 背板 自适应 通信接收机 SerDes 自动增益控制
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参考文献9

  • 1Optical Interconnect Forum.Common Electrical I/O ( CEI)-Electrical and Jitter Interoperability agreements for 6G+bps and 11G + bps I/O. http://www. oiforum. com/public/documents/OIFCEI _ 02. 0. pdf . 2005
  • 2Song W,Ramaswamy S,Bhakta B.Design of a 6. 25 Gbps backplane SerDes with TOP-down design methodology[].Proceedings of the DesignCon East.2004
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