非规则低密度奇偶校验码译码器的结构设计和优化

Irregular Low Density Parity Check Decoder Design and Its Optimized Decoding Process

提出了一种通用的非规则低密度奇偶校验码译码器,可适用于通过单位阵准循环移位扩展构造的任意行重非规则LDPC码.该译码器通过调整译码存储单元的存储内容而节省了一个交织网络.同时,针对处理非规则LDPC码译码过程中由行列重差异所引起的流水冲突,提出了优化的插入空闲等待时钟周期方法以及预处理方法,有效地避免了流水冲突,从而保证了该译码器的高吞吐量以及译码性能.

This paper proposed an improved decoder structure which can be applied to any irregular quasicyclic low density parity check （LDPC） codes. The decoder needs only one shuffle network by adjusting the memory cells of the RAM. The pipeline conflicts due to the irregular LDPC codes can be solved by properly inserting idle clocks and preprocess of the low density parity check matrix. Meanwhile, such decoding process still achieves high throughput and suffers little decoder performance loss.