基于射极耦合逻辑的数字延迟系统

An emitter coupled logic based digital delay system

利用射极耦合逻辑(ECL)转换速度快、延迟小、可靠性强等特点,提出了一种新颖的数字延迟系统实现方案。现场可编程门阵列(FPGA)输出的LVTTL电平信号作为系统的输入触发信号,经过电平转换传输给8位数字可编程延迟芯片AD9500。AD9500的延迟输出再经过电平转换,以LVTTL电平信号作为系统终端的输出形式。在信号传输过程中,系统采用差分方式,并对传输信号做了端接处理,增强了高速信号的抗干扰性。测试结果显示系统实现了分辨率为100 ps的数字延迟。

This paper presented a novel digital delay system based on such positives as high conversion rate, low delay and high reliability of emitter coupled logic （ECL）. The LVTTL signal ,which was the output of FPGA and served as the input trigger signal, was transmitted to AD9500 after level conversion. The delayed output signal of AD9500 was converted back to LVTTL signal to be the ouput signal of the system terminal. Differential signal served as the input of the system, and terminal circuit was employed to process the transmitted signal. Test results show that the system achieves a delay resolution of 100 ps.