功率快恢复二极管反偏ESD机理分析

Mechanism Analysis on Reverse Biased ESD of Power Fast Recovery Diodes

功率半导体器件静电放电(ESD)的可靠性在应用中至关重要,其抗ESD的机理需深入研究。采用一种符合GB/T 17626.2标准的简明分段线性电流源,对功率快恢复二极管(FRD)反偏ESD过程进行仿真计算。基于器件外端电压波形经历过冲、负阻和振荡以及平缓发展三个阶段,分析了器件内部相应的一系列复杂变化。结果表明:器件内部的"过耗尽"、雪崩注入、载流子及电场分布涨落等变化,最终导致电流在pn结拐角处形成局部集中。最后,分析了器件结构参数对抗ESD能力的影响。

Electrostatic discharge （ESD） reliability plays a crucial role in the application of power semiconductor device, so it is important to research the mechanism of ESD immunity. A simple piecewiselinear current-source method fulfilled the national standard GB/T 17626. 2 was proposed and used in the simulation of reverse biased ESD process of power fast recovery diodes. A sequence of complex evolution was discussed in the inner device during three stages of the terminal voltage waveform, including over-shoot, negative differential resistance in oscillation and stably developing. The results show that the local current crowds in the corner of pn junction due to the complex evolution such as over-depletion, avalanche injection, the fluctuation of carriers and electric field distribution, etc. Finally, the impacts of device structure parameters on the ESD immunity are investigated.