摘要
A memory compress algorithm for 12\|bit Arbitrary Waveform Generator (AWG) is presented and optimized. It can compress waveform memory for a sinusoid to 16×13bits with a Spurious Free Dynamic Range (SFDR) 90.7dBc (1/1890 of uncompressed memory at the same SFDR) and to 8×12bits with a SFDR 79dBc. Its hardware cost is six adders and two multipliers. Exploiting this memory compress technique makes it possible to build a high performance AWG on a chip.
A memory compress algorithm for 12\|bit Arbitrary Waveform Generator (AWG) is presented and optimized. It can compress waveform memory for a sinusoid to 16×13bits with a Spurious Free Dynamic Range (SFDR) 90.7dBc (1/1890 of uncompressed memory at the same SFDR) and to 8×12bits with a SFDR 79dBc. Its hardware cost is six adders and two multipliers. Exploiting this memory compress technique makes it possible to build a high performance AWG on a chip.
关键词
随机波形产生器
存储器
压缩算法
arbitrary waveform generator
direct digital synthesis
memory compress algorithm
