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Hardware Optimization Technique of Full-Customized HW/SW Co-Design 被引量：1

全定制软/硬件协同设计中的硬件优化技术(英文)
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摘要 The hardware optimization technique of mono similarity system generation is presented based on hardware/software(HW/SW) co design.First,the coarse structure of sub graphs' matching based on full customized HW/SW co design is put forward.Then,a universal sub graphs' combination method is discussed.Next,a more advanced vertexes' compression algorithm based on sub graphs' combination method is discussed with great emphasis.Experiments are done successfully with perfect results verifying all the formulas and the methods above. 提出了基于单相似系统生成的软 /硬件协同设计中的硬件优化技术 .介绍了一种基于子图匹配软 /硬件协同设计技术的大致框架 ,引进通用子图群合并算法 ,并着重讨论了基于节点压缩优化技术的高效子图群合并算法 .
作者 汤磊 魏少军 仇玉林
机构地区 中国科学院微电子中心 清华大学微电子所
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2002年第6期637-644,共8页 半导体学报（英文版）
基金 国家自然科学基金资助项目 (批准号 :696760 2 4)
关键词 HW/SW co design CDFG mono similarity system sub graph compound graph COMBINE usage degree cost 硬件优化 软/硬件协同设计 CDFG 单相似系统 复合图 图群合并算法
分类号 TN402 [电子电信—微电子学与固体电子学]
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参考文献6

  • 1Eles Petru,Peng Zebo.Systemsynthesis with VHDL.Kluwer Academic Publishers,1998:63
  • 2Liu Huiqun,Wong D F.Integrated partitioning and scheduling for HW/SWco-design.Proceedings of Codes/CASH'98,1998:609
  • 3Bianco Luc,Auguin Michel,Gogniat Guy,et al.A path analysis based partitioning fortime constrained embedded systems.Proceedings of Codes/CASH'98,1998:85
  • 4Gogniat Guy,Auguin Michel,Bianco Luc,et al.Communication synthesis and HW/SWintegration for embedded system design.Proceedings of Codes/CASH'98,1998:49
  • 5Saha D,Mitra R S,Basu Anupam.Hardware software partitioning using geneticalgorithm.Proceedings of the 10th International Conference on VLSI Design,1997:155
  • 6Pop Paul,Eles Petru,Peng Zebo.Scheduling with optimized communication fortime-triggered embedded systems.Proceedings of Codes/CASH'99,1999:178

同被引文献5

  • 1GUPTA R K, MICHELI D G. Hardware-software cosynthesis for digital systems[J]. IEEE Design and Test of Computers, 1993,10(3) : 29-41.
  • 2WOLF W. A decade of hardware/software codesign [J]. Computer, 2003,36(4) :38-41.
  • 3WOLF W H. Architectural co-synthesis algorithm for distributed, embedded computing systems [J]. IEEE Trans Very Large Scale Integr Syst, 1997, 5 (2): 218-229.
  • 4ASCIA G, CATANIA V, PALESI M. A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip [ J ]. IEEE Trans Comp Aid Des Integr Circs and Syst, 2005, 24 (4): 635-644.
  • 5HAN Muhua, LIU Leibo, WEI Shaojun. A graph covering method for template based system partition [C] // Proc Int Conf Commun, Cite and Syst. Xiamen,China. 2008 : 1502-1505.

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Journal of Semiconductors
2002年 第6期

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