摘要
提出了一种基于FPGA和DDR II的JPEG图像压缩模式。在此基础上完成了A3高速光电扫描仪的设计与实现,解决了高速扫描仪中硬件资源与扫描速度相互制约的问题。通过内外存储器流水式复用模型,在降低片上RAM消耗的同时构建灵活、快速的大数据量存储与传输模式。采用高效的分时复用数据链路实现JPEG图像压缩,进一步提高硬件模块的压缩和传输速度。对采用中低端FPGA芯片设计的A3高速扫描仪的测量结果表明,在300dpi分辨率下扫描A3幅面纸张的速度可达140面/min,扫描延时小于1ms,压缩前后峰值信噪比高达86.9dB,完全满足高端高速扫描仪的要求。该模式的实现极大地降低了高端高速光电扫描仪对于硬件资源的要求,也可推广应用到其它幅面的高速光电扫描仪中。
A JPEG image compression method based on FPGA and DDR II is proposed. The A3 high-speed scanner is designed and realized. The issue of mutual restraint between the hardware resource and the scanning speed in the high-speed scanner is solved. Basic principle is to build flexible, fast large amount of data storage and transmission mode while reducing the consumption of on-chip RAM through the internal and external storage type water reuse model. And using an efficient time-multiplexed data link to implement the JPEG image compression further improves the compression and transmission speed of hardware module. Theoretical analysis and experimental results show that using the A3 high-speed scanner designed with low-end FPGA chip, the speed of scanning A3 wide paper under a 300dpi resolution can reach 140 page per minute, scanning time delay is less than 1ms, peak signal noise ratio as high as 86.9dB before and after compression, and this fully meets the requirements of high-end high-speed scanners. The high-speed scanners for hardware resource requirements are greatly reduced under the implementation of the model, and this model can also be promoted to apply in other high-speed scanner with different format.
出处
《计量学报》
CSCD
北大核心
2016年第2期133-137,共5页
Acta Metrologica Sinica
基金
国家自然科学基金(61205004)
粤港关键领域重点突破项目(东科2012205106,东科20091683)