基于VMM的FPGA软件可重用验证平台

FPGA Software Verification Platform Based on VMM

传统的验证平台编写复杂,且难以在不同设计之间重用。采用System Verilog支持的VMM验证方法学,并结合带约束的随机验证和覆盖率驱动的验证技术,构建可重用验证平台,完成被测FPGA软件的验证。与直接测试方法相比,该验证平台不仅能够有效提高验证效率,而且在模块级和系统级验证过程中,能够重用该验证平台或验证组件。

Traditional verification platform is complex, and it is difficult to reuse between different designs. I ne patiorm uses VMM, verification methodology supported by SystemVerilog, and with the combination of random verification and coverage driven verification technology, to build a reusable verification platform to complete the test FPGA software verification. Compared with the direct test method, the verification platform can not only improve the verification efficiency, but also can reuse the verification platform or the verification component in the process of module level and system level verification.