三维堆叠封装TSV互连结构热扭耦合应力分析与优化

Analysis and optimization of thermal-torsional coupling stress of 3D stacked packaged TSV interconnect structure

建立了三维硅通孔(TSV)芯片垂直堆叠封装结构有限元分析模型,对模型在热扭耦合加载下进行了仿真分析;分析了TSV材料参数与结构参数对TSV互连结构热扭耦合应力的影响;采用了响应面与模拟退火算法对在热扭耦合加载下TSV互连结构参数进行优化设计。结果表明:TSV互连结构最大热扭耦合应力应变位于铜柱与微凸点接触面外侧;微凸点材料为SAC387时,TSV互连结构热扭耦合应力最大,该应力随SiO_(2)层厚度的增大而增大,随铜柱直径的增大而先增大后减小,随铜柱高度的增大而减小;最优参数水平组合为铜柱直径50μm、铜柱高度85μm、SiO_(2)层厚度3μm,优化后的最大热扭耦合应力下降了5.3%。

Finite element analysis model was established for a three-dimensional through-silicon via(TSV)chip with vertically stacked packaging structure.Simulation was performed with the model to analyze the thermal-torsional coupling loading.Analysis was implemented to understand the effects of material and structural parameters on the thermal-torsional coupling stress of the TSV interconnect structure.The response surface and simulated annealing algorithms were used to optimize the design of the TSV interconnect structure parameters under thermal-torsional coupling loading.The results show that the maximum thermal-torsional coupling stress and strain of the TSV interconnect structure are located outside the contact surface between the copper pillar and the micro-bump.When the micro-bump material is SAC387,the thermal-torsional coupling stress is the largest.The stress increases with the thickness of the SiO_(2)layer.The stress first increases and then decreases with the diameter of copper pillar,which monotonously decreases with pillar height.The optimized parameters are as follow:Copper pillar diameter about 50μm,pillar height about 85μm,and SiO_(2)layer thickness about 3μm,which reduces the maximum thermal-torsional coupling stress by 5.3%.